The present invention relates generally to field effect transistor (FET) devices, and more specifically, to FinFET devices.
Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFET), in which a gate structure is energized to create an electric field in an underlying channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body.
Complementary metal-oxide-semiconductor field-effect transistors, which are typically referred to as CMOS devices, have become widely used in the semiconductor industry. These CMOS devices include both n-type and p-type (NMOS and PMOS) transistors, and therefore promote the fabrication of logic and various other integrated circuitry.
The escalating demands for high density and performance associated with ultra large scale integrated (ULSI) circuit devices have required certain design features, such as shrinking gate lengths, high reliability and increased manufacturing throughput. The continued reduction of design features has challenged the limitations of conventional fabrication techniques. Three-dimensional semiconductor devices, such as fin-type semiconductor devices (referred to as finFETs), typically include dielectric gate spacers formed on sidewalls of the gate stack to isolate the gate stack from the adjacent source/drain (S/D) regions.
FinFET devices include an arrangement of fins disposed on a substrate. The fins are formed from a semiconductor material. A gate stack is arranged over the fins and defines a channel region of the fins, while regions of the fins extending outwardly from the channel region define active source and drain regions of the device.
Previous methods for patterning the fins included depositing or thermally growing a hardmask layer of an oxide material over a layer of semiconductor material and depositing a lithographic mask over the hardmask layer. The fins are formed by removing exposed portions of the hardmask layer and the semiconductor material resulting in an arrangement of fins having a hardmask layer arranged on the semiconductor material that is disposed on an insulator layer of the substrate.
As the scale of features in finFET devices continues to scale down through successive technology development nodes, challenges emerge for the design of processes to achieve the desired critical dimensions of required features in the finished finFET device.